1. Field of the Invention
The present invention relates to a method and a device for decoding a BPSK (xe2x80x9cBinary Phase Shift Keyingxe2x80x9d) coded pulsed signal, i.e. coded by phase jumps.
The present invention particularly relates to decoding BPSK coded data sent by a contactless smart card, and the production of a contactless smart card read head that is simple in structure and inexpensive.
In accordance with draft standard ISO 14443, a contactless smart card operating by electromagnetic induction sends out data in the form of a BPSK coded signal. The coded signal is a subcarrier of a frequency of 847 KHz obtained by dividing the frequency of 13.56 MHz of the ambient magnetic field given off by a read head of the smart card. A bit is coded by a defined number of subcarrier cycles, and a change of the value of a bit, in relation to the previous bit, is coded by an inversion of the subcarrier phase. Upon receipt, the coded signal appears like a pulsed signal composed of pulses that have a duty factor of 0.5 and phase jumps. The detection of phase jumps allows the value of the bits sent by the smart card to be deduced.
In previous practices, a BPSK coded signal is usually decoded by means of a phase-locked loop PLL, the main component of which is a voltage-controlled oscillator VCO. However, a phase-locked loop is a rather costly complex circuit compared to the other components of a contactless smart card read head.
2. Discussion of the Related Art
An example of a phase-locked demodulation circuit is represented in FIG. 4 of application DE 34,24,623 or its equivalent, U.S. Pat. No. 4,608,540, and the circuit represented comprises a phase-locked loop comprising an oscillator VCO [10] and a loop filter [13].
Another classical technique for decoding a BPSK coded signal includes sampling and processing the signal by means of a digital algorithm. However, the sampling and processing of a signal at 847 KHz require a high sampling frequency and a fast microprocessor that also has the disadvantage of being rather costly.
Various sampling demodulation circuits are also described in application DE 34,24,623 or its equivalent, U.S. Pat. No. 4,608,540 (aforementioned), particularly in relation with FIGS. 5, 7 and 11 of these documents.
Finally, U.S. Pat. No. 5,640,427 describes, in relation with its FIG. 1, a coherent demodulator of MDPSK or 2PSK coded signals comprising an oscillator [16] delivering two signals LO_I and LO_Q phase shifted by 90xc2x0. The signals LO_I and LO_Q are logically combined with a signal to be demodulated IF, to produce two activation signals of two counters [32, 34] controlled by a counting clock the frequency of which is equal to N times the frequency F_IF of the signal IF to be demodulated. The outputs of the counters are processed by a computer [36] provided to implement various mathematical relations described in this document.
The object of the present invention is to provide a BPSK decoding method that can be implemented by means of simple and inexpensive components, particularly to produce a small, low-cost, contactless smart card read head.
This object is achieved by providing a method for decoding a pulsed signal coded by phase jumps, in which a bit is coded by N pulses of the coded signal and a change of the value of a bit in relation to the previous bit is coded by an inversion of the coded signal phase, a method comprising steps of: sampling the coded pulsed signal by means of a pulsed strobe of the same frequency as the coded signal, with a sampling window the duration of which is less than the duration of one pulse of the coded signal, and for each group of N pulses of the coded signal, counting the number of sampled pulses resulting from the sampling of the coded signal and assigning to the bit coded by the group of N pulses a logic value which is a function of the number of sampled pulses counted.
According to one embodiment, a first logic value is assigned to a bit when the number of sampled pulses is higher than or equal to a predefined number, and a second logic value is assigned to a bit when the number of sampled pulses is lower than the aforementioned predefined number.
According to one embodiment, the predefined number is equal to half the number N of bit coding pulses.
According to one embodiment, the coded signal is sampled by combining the coded signal and the strobe by means of the logic function AND, the strobe being composed of pulses of a shorter duration than the pulses of the coded signal, each defining a sampling window.
According to one embodiment, the method comprises a strobe synchronisation step aiming at setting the pulses of the strobe to the pulses of a start bit.
Preferably, the synchronisation step is carried out during the receipt of at least one synchronisation bit preceding the start bit, the value of which is the opposite of that of the start bit, and includes adjusting the strobe phase so that no sampled pulse appears.
The present invention also relates to a device for decoding a pulsed signal coded by phase jumps, the coding including coding a bit by N pulses of the coded signal and coding a change of the value of a bit in relation to the previous bit by an inversion of the coded signal phase, device comprising decoding means arranged to sample the coded pulsed signal by means of a pulsed strobe of the same frequency as the coded signal, with a sampling window the duration of which is less than the duration of a coded signal pulse, delivering a sampled signal, and for each group of N pulses of the coded signal, counting the number of sampled pulses resulting from the sampling of the coded signal and assigning a logic value to the bit coded by the group of N pulses which is a function of the number of sampled pulses counted.
According to one embodiment, the decoding means are arranged to assign a first logic value to a bit when the number of sampled pulses is higher than or equal to a predefined number, and to assign a second logic value to a bit when the number of sampled pulses is lower than the aforementioned predefined number.
According to one embodiment, the predefined number used by the decoding means is equal to half the number N of bit coding pulses.
According to one embodiment, the decoding means are arranged to sample the coded signal by combining the coded signal and the strobe by means of the logic function AND, the strobe being composed of pulses of a shorter duration than the pulses of the coded signal, each defining a sampling window.
According to one embodiment, the decoding means are arranged to carry out a strobe synchronisation step aiming at setting the pulses of the strobe to the pulses of a start bit.
According to one embodiment, the decoding means are arranged to carry out the synchronisation step during the receipt of at least one synchronisation bit preceding the start bit, the value of which is the opposite of that of the start bit, by adjusting the strobe phase so that no sampled pulse appears.
According to one embodiment, the device comprises a pulse width modulator to deliver the strobe, a sampler receiving the coded signal and the strobe at input, delivering a sampled signal, a counter receiving the sampled signal at its counting input, to count the number of sampled pulses resulting from the sampling of the coded signal, and a means for reading the output of the counter and for assigning a logic value to a bit coded by a group of N pulses which is a function of the number of sampled pulses counted by the counter.
According to one embodiment, the device comprises means for receiving the coded pulsed signal by inductive coupling.
The present invention also relates to a contactless smart card reader, comprising a device according to the present invention.